
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SMotor is
    Port ( CLK : in  STD_LOGIC;
			  sentido : in std_logic;
			  Numero_Pasos : in STD_LOGIC_VECTOR (29 downto 0);
			  Interrupcion : out STD_LOGIC := '0';
           Ss : out  STD_LOGIC_VECTOR (3 downto 0) := "0000"
			 );
end SMotor;

architecture ArqSMotor of SMotor is

signal aux: std_logic_vector(1 downto 0) := "00";


signal contador: integer range 0 to 536870999 := 0;

begin

process(CLK)
begin
	if rising_edge(CLK) then
	
	
	
			if contador < conv_integer(Numero_Pasos) then
					if sentido = '0' then
						if aux="00" then
							aux <= "01"; 
							Ss <= not("1100"); 
						elsif aux="01" then
							aux <= "10";
							Ss <= not("0110");
						elsif aux="10" then
							aux <= "11";
							Ss <= not("0011");
						else
							aux <= "00";
							Ss <= not("1001");
						end if;
						contador <= contador + 1;
					else
						if aux="00" then
							aux <= "01"; 
							Ss <= not("1001"); 
						elsif aux="01" then
							aux <= "10";
							Ss <= not("0011");
						elsif aux="10" then
							aux <= "11";
							Ss <= not("0110");
						else
							aux <= "00";
							Ss <= not("1100");
						end if;
						contador <= contador + 1;
					end if; 
					Interrupcion <= '0';
			else
				Interrupcion <= '1';
				contador <= 0;
			end if;
			
			
	end if;
end process;


end ArqSMotor;

